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19-4368; Rev 0; 11/08
Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface
General Description
The MAX5500/MAX5501 integrate four low-power, 12-bit digital-to analog converters (DACs) and four precision output amplifiers in a small, 20-pin package. Each negative input of the four precision amplifiers is externally accessible providing flexibility in gain configurations, remote sensing, and high output drive capacity, making the MAX5500/MAX5501 ideal for industrial-process-control applications. Other features include software shutdown, hardware shutdown lockout, an active-low reset which clears all registers and DACs to zero, a user-programmable logic output, and a serial-data output. Each DAC provides a double-buffered input organized as an input register followed by a DAC register. A 16-bit serial word loads data into each input register. The serial interface is compatible with SPITM/QSPITM/ MICROWIRETM. The serial interface allows the input and DAC registers to be updated independently or simultaneously with a single software command. The 3-wire interface simultaneously updates the DAC registers. All logic inputs are TTL/CMOS-logic compatible. The MAX5500 operates from a single +5V power supply, and the MAX5501 operates from a single +3V power supply. The MAX5500/MAX5501 are specified over the extended -40C to +105C temperature range.
Features
Four 12-Bit DACs with Configurable Output Amplifiers +5V or +3V Single-Supply Operation Low Supply Current: 0.85mA Normal Operation 10A Shutdown Mode (MAX5500) Force-Sense Outputs Power-On Reset Clears All Registers and DACs to Zero Capable of Recalling Last State Prior to Shutdown SPI/QSPI/MICROWIRE Compatible Simultaneous or Independent Control of DACs through 3-Wire Serial Interface User-Programmable Digital Output Guaranteed Over Extended Temperature Range (-40C to +105C)
MAX5500/MAX5501
Ordering Information
PART MAX5500AGAP+ MAX5500BGAP+ MAX5501AGAP+* MAX5501BGAP+* PINPACKAGE 20 SSOP 20 SSOP 20 SSOP 20 SSOP INL (LSB) 0.75 2 0.75 2 SUPPLY (V) +5 +5 +3 +3
Applications
Industrial Process Controls Automatic Test Equipment Microprocessor (P)-Controlled Systems Motion Control Digital Offset and Gain Adjustment Remote Industrial Controls
+Denotes a lead-free/RoHS-compliant package. *Future product--contact factory for availability.
Note: All devices are specified over the -40C to +105C operating temperature range. Pin Configuration appears at end of data sheet.
Functional Diagram
DOUT CL PDL DGND AGND VDD REFAB FBA OUTA FBB OUTB DAC B FBC OUTC DAC C FBD OUTD DAC D
DECODE CONTROL INPUT REGISTER A DAC REGISTER A DAC A
MAX5500 MAX5501
16-BIT SHIFT REGISTER
INPUT REGISTER B
DAC REGISTER B
INPUT REGISTER C
DAC REGISTER C
SR CONTROL CS DIN SCLK
LOGIC OUTPUT UPO
INPUT REGISTER D
DAC REGISTER D
REFCD
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor, Corp.
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________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX5500/MAX5501
ABSOLUTE MAXIMUM RATINGS
VDD to AGND............................................................-0.3V to +6V VDD to DGND ...........................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V REFAB, REFCD to AGND ...........................-0.3V to (VDD + 0.3V) OUT_, FB_ to AGND...................................-0.3V to (VDD + 0.3V) Digital Inputs to DGND.............................................-0.3V to +6V DOUT, UPO to DGND ................................-0.3V to (VDD + 0.3V) Continuous Current into Any Pin.......................................20mA Continuous Power Dissipation (TA = +70C) 20-Pin SSOP (derate 8.00mW/C above +70C) .........640mW Operating Temperature Range .........................-40C to +105C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(MAX5500 (VDD = +5V 10%, VREFAB = VREFCD = 2.5V), MAX5501 (VDD = +3V 10%, VREFAB = VREFCD = 1.5V), VAGND = VDGND = 0, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values at TA = +25C. Output buffer connected in unitygain configuration (Figure 9).)
PARAMETER Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity Offset Error Offset-Error Tempco Gain Error Gain-Error Tempco Power-Supply Rejection Ratio Gain Error Offset Error Integral Nonlinearity REFERENCE INPUT Reference Input Range Reference Input Resistance Reference Current in Shutdown DIGITAL INPUTS Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance VIH VIL IIN CIN VIN = 0 or VDD 0.1 8 MAX5500A/MAX5500B MAX5501A/MAX5501B 2.4 2.0 0.8 1.0 V V A pF VREF RREF Code-dependent, minimum at code 555H 0 8 0.01 1.0 VDD - 1.4 V k A PSRR GE VOS INL (Note 1) MATCHING PERFORMANCE (TA = +25oC) -0.3 1.0 0.35 2.0 3.5 1.0 LSB mV LSB GE (Note 1) SYMBOL N INL DNL VOS 6 -0.3 1 100 600 2.0 MAX5500A/MAX5501A MAX5500B/MAX5501B Guaranteed monotonic CONDITIONS MIN 12 0.25 0.75 2.0 1.0 3.5 TYP MAX UNITS Bits LSB LSB mV ppm/ oC LSB ppm/ oC V/V
STATIC PERFORMANCE (Analog Section)
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Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(MAX5500 (VDD = +5V 10%, VREFAB = VREFCD = 2.5V), MAX5501 (VDD = +3V 10%, VREFAB = VREFCD = 1.5V), VAGND = VDGND = 0, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values at TA = +25C. Output buffer connected in unitygain configuration (Figure 9).)
PARAMETER DIGITAL OUTPUTS Output High Voltage Output Low Voltage DYNAMIC PERFORMANCE Voltage Output Slew Rate SR To 0.5 LSB, VSTEP = 2.5V MAX5500A/MAX5500B Output Settling Time To 0.5 LSB, VSTEP = 2.5V MAX5501A/MAX5501B Output Voltage Swing Current into FB_ OUT_ Leakage Current in Shutdown Startup Time Exiting Shutdown Mode Digital Feedthrough Digital Crosstalk POWER SUPPLIES Supply Voltage Supply Current Supply Current in Shutdown Reference Current in Shutdown TIMING CHARACTERISTICS (Figure 6) SCLK Clock Period SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time DIN Setup Time DIN Hold Time tCP tCH tCL tCSS tCSH tDS tDH 100 40 40 40 0 40 0 ns ns ns ns ns ns ns VDD IDD MAX5500A/MAX5500B MAX5501A/MAX5501B (Note 3) (Note 3) (Note 3) 4.5 3.0 0.85 10 10 5.5 3.6 1.1 20 20 V mA A A RL = MAX5500A/MAX5500B MAX5501A/MAX5501B CS =VDD, fIN = 100kHz Rail-to-rail (Note 2) 16 0 to VDD 0 0.01 15 20 5 5 0.1 1.0 V A A s nV*s nV*s 0.6 12 s V/s VOH VOL ISOURCE = 2mA ISINK = 2mA VDD - 0.5 0.13 0.4 V V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5500/MAX5501
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Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX5500/MAX5501
ELECTRICAL CHARACTERISTICS (continued)
(MAX5500 (VDD = +5V 10%, VREFAB = VREFCD = 2.5V), MAX5501 (VDD = +3V 10%, VREFAB = VREFCD = 1.5V), VAGND = VDGND = 0, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values at TA = +25C. Output buffer connected in unitygain configuration (Figure 9).)
PARAMETER SCLK Rise to DOUT Valid Propagation Delay SCLK Fall to DOUT Valid Propagation Delay SCLK Rise to CS Fall Delay CS Rise to SCLK Rise Hold Time CS Pulse-Width High SYMBOL tD01 tD02 tCS0 tCS1 tCSW CONDITIONS CLOAD = 200pF CLOAD = 200pF 40 40 100 MIN TYP MAX 80 80 UNITS ns ns ns ns ns
Note 1: Guaranteed from code 11 to code 4095 in unity-gain configuration. Note 2: Accuracy is better than 1.0 LSB for VOUT = 6mV to (VDD - 60mV), guaranteed by PSR test on endpoints. Note 3: RL = , digital inputs at DGND or VDD.
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE
MAX5500 toc01
INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE
MAX5500 toc02
SUPPLY CURRENT vs. TEMPERATURE
MAX5500 VDD = 5V
MAX5500 toc03
0.2 0 -0.2 INL (LSB)
MAX5500 VDD = 5V RL = 5k
0 -0.2
MAX5501 VDD = 3V RL = 5k
910 900 890
INL (LSB)
-0.4 -0.6 -0.8 -1.0
IDD (A)
-0.4 -0.6 -0.8 -1.0 0.4 1.2 2.0 2.8 3.6 4.4 REFERENCE VOLTAGE (V)
880 870 860 CODE = FFF hex 850
0.4
0.9
1.4
1.9
2.4
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
REFERENCE VOLTAGE (V)
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Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
820 810 800 INL (LSB) INL (LSB) IDD (A) 790 780 770 760 750 740 730 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) CODE = FFF hex -4 -4 -2 -2 MAX5501 VDD = 3V
MAX5500 toc04
MAX5500/MAX5501
FULL-SCALE ERROR vs. LOAD
MAX5500 toc05
FULL-SCALE ERROR vs. LOAD
MAX5501 VDD = 3V
MAX5500 toc06
830
0 MAX5500 VDD = 5V
0
-1
-1
-3
-3
-5 0.01 0.1 1 LOAD (k) 10 100
-5 0.01 0.1 1 LOAD (k) 10 100
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5500 toc07
SUPPLY CURRENT vs. SUPPLY VOLTAGE
796 794 IDD (A) 792 790 788 786 784 CODE = FFF hex 782 MAX5501 VDD = 3V
MAX5500 toc08
ANALOG CROSSTALK 5V
MAX5500 toc09
940 920 900 880 IDD (A) 860 840 820 800 780 760
MAX5500 VDD = 5V
798
OUTA 1V/div
OUTB AC-COUPLED 10mV/div
CODE = FFF hex 4.50 4.75 5.00 VDD (V) 5.25 5.50 3.0 3.1
3.2
3.3 VDD (V)
3.4
3.5
3.6
10s/div VREF = 2.5V, RL = 5k, CL = 100pF DACA CODE SWITCHING FROM 00C hex TO FCC hex DACB CODE SET TO 800 hex
ANALOG CROSSTALK 3V
MAX5500 toc10
DYNAMIC RESPONSE 5V
MAX5500 toc11
OUTA 0.5V/div OUTA 1V/div
OUTB AC-COUPLED 50mV/div
10s/div VREF = 1.5V, RL = 5k, CL = 100pF DACA CODE SWITCHING FROM 00C hex TO FFF hex DACB CODE SET TO 800 hex
10s/div VREF = 2.5V, RL = 5k, CL = 100pF SWITCHING FROM CODE 000 hex TO FB4 hex OUTPUT AMPLIFIER GAIN = +2
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Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX5500/MAX5501
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
DIGITAL FEEDTHROUGH 3V (SCLK = 100kHz)
MAX5500 toc13
DYNAMIC RESPONSE 3V
MAX5500 toc12
DIGITAL FEEDTHROUGH 5V (SCLK = 100kHz)
MAX5500 toc14
OUTA 0.5V/div SCLK 1V/div OUTA AC-COUPLED 10mV/div
SCLK 2V/div
OUTA AC-COUPLED 10mV/div
10s/div VREF = 1.5V, RL = 5k, CL = 100pF SWITCHING FROM CODE 000 hex TO FB4 hex OUTPUT AMPLIFIER GAIN = +1
4s/div VREF = 1.5V, RL = 5k, CL = 100pF VCS = VPDL = VCL = 3.3V, VDIN = 0V DACA CODE SET TO 800 hex
2s/div VREF = 2.5V, RL = 5k, CL = 100pF VCS = VPDL = VCL = 5V, VDIN = 0V DACA CODE SET TO 800 hex
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NAME AGND FBA OUTA OUTB FBB REFAB CL CS DIN SCLK DGND DOUT UPO PDL REFCD FBC OUTC OUTD FBD VDD Analog Ground DAC A Output Amplifier Feedback DAC A Output Voltage DAC B Output Voltage DAC B Output Amplifier Feedback DAC A/DAC B Reference Voltage Input Active-Low Clear Input. CL clears all DACs and registers. CL resets all outputs (OUT_, UPO, and DOUT) to 0. Active-Low Chip-Select Input Serial Data Input Serial Clock Input Digital Ground Serial Data Output User-Programmable Logic Output Active-Low Power-Down Lockout. Drive PDL low to lock out software shutdown. DAC C/DAC D Reference Voltage Input DAC C Output Amplifier Feedback DAC C Output Voltage DAC D Output Voltage DAC D Output Amplifier Feedback Positive Power Supply FUNCTION
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Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface
Detailed Description
The MAX5500/MAX5501 integrate four 12-bit, voltageoutput digital-to-analog converters (DACs) that are addressed through a simple 3-wire serial interface. The devices include a 16-bit data-in/data-out shift register. Each internal DAC provides a doubled-buffered input composed of an input register and a DAC register (see the Functional Diagram). The negative input of each amplifier is externally accessible. The DACs are inverted rail-to-rail ladder networks that convert 12-bit digital inputs into equivalent analog output voltages in proportion to the applied reference voltage inputs. DACs A and B share the REFAB input, while DACs C and D share the REFCD input. The two reference inputs allow different full-scale output voltage ranges for each pair of DACs. Figure 1 shows a simplified circuit diagram of one of the four DACs. of 555 hex, to a high value exceeding giga-ohms with an input code of 000 hex. The load regulation of the reference source affects the performance of the devices as the input impedance at the reference inputs is code dependent. The REFAB and REFCD reference inputs provide a 10k guaranteed minimum input impedance. When the same voltage source drives the two reference inputs, the effective minimum impedance is 5k. A voltage reference with an excellent load regulation of 0.0002mV/mA, such as the MAX6033, is capable of driving both reference inputs simultaneously at 2.5V. Driving REFAB and REFCD separately improves reference accuracy. The REFAB and REFCD inputs enter a high-impedance state, with a typical input leakage current of 0.02A, when the MAX5500/MAX5501 are in shutdown. The reference input capacitance is also code dependent and typically ranges from 20pF with an input code of all 0s to 100pF with an input code of all 1s.
MAX5500/MAX5501
Reference Inputs
The two reference inputs accept positive DC and AC signals. The voltage at each reference input sets the full-scale output voltage for the two corresponding DACs. The reference input voltage range is 0V to (VDD - 1.4V). The output voltages (VOUT_) are represented by a digitally programmable voltage source as: VOUT_ = (VREF x NB/4096) x Gain where NB is the numeric value of the binary input code (0 to 4095) of the DAC. VREF is the reference voltage. Gain is the externally set voltage gain. The impedance at each reference input is code-dependent, ranging from a low value of 10k when both DACs connected to the reference accept an input code
FB_
Output Amplifiers
All DAC outputs are internally buffered by precision amplifiers with a typical slew rate of 0.6V/s. Access to the inverting input of each output amplifier provides the greater flexibility in output gain setting/signal conditioning (see the Applications Information section). With a full-scale transition at the output, the typical settling time to within 0.5 LSB is 12s when the output is loaded with 5k in parallel with 100pF. A load of less than 2k at the output degrades performance. See the Typical Operating Characteristics for the output dynamic responses and settling performances of the amplifiers.
Power-Down Mode
The MAX5500/MAX5501 feature a software-programmable shutdown that reduces supply current to a typical value of 10A. Drive PDL high to enable the shutdown mode. Write 1100XXXXXXXXXXXX as the input-control word to put the device in power-down mode (Table 1). In power-down mode, the output amplifiers and the reference inputs enter a high-impedance state. The serial interface remains active. Data in the input registers is retained in power-down, allowing the devices to recall the output states prior to entering shutdown. Start up from power-down either by recalling the previous configuration or by updating the DACs with new data. Allow 15s for the outputs to stabilize when powering up the devices or bringing the devices out of shutdown.
R
R
R
OUT_
2R
2R D0
2R D9
2R D10
2R D11
REF_ AGND
SHOWN FOR ALL 1s ON DAC
Figure 1. Simplified DAC Circuit Diagram
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Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX5500/MAX5501
Serial-Interface Configurations
The MAX5500/MAX5501s' 3-wire serial interface is compatible with both MICROWIRE (Figure 2) and SPI/QSPI (Figure 3). The serial input word consists of two address bits and two control bits followed by 12 data bits (MSB first), as shown in Figure 4. The 4-bit address/control code determines the MAX5500/ MAX5501s' response outlined in Table 1. The connection between DOUT and the serial-interface port is not necessary, but may be used for data echo. Data held in the shift register can be shifted out of DOUT and returned to the P for data verification. The digital inputs of the MAX5500/MAX5501 are double buffered. Depending on the command issued through the serial interface, the input register(s) can be loaded without affecting the DAC register(s), the DAC register(s) can be loaded directly, or all four DAC registers can be updated simultaneously from the input registers (Table 1). bits (C1, C0), followed by the 12 data bits D11-D0 (Figure 4). The 4-bit address/control code determines: * The register(s) to be updated * The clock edge on which data is to be clocked out through the serial-data output (DOUT) * The state of the user-programmable logic output (UPO) * If the device is to enter shutdown mode (assuming PDL is high) * How the device is configured when exiting out of shutdown mode
+5V
Serial-Interface Description
The MAX5500/MAX5501 require 16 bits of serial data. Table 1 lists the serial-interface programming commands. For certain commands, the 12 data bits are don't-care bits. Data is sent MSB first and can be sent in two 8-bit packets or one 16-bit word (CS must remain low until 16 bits are transferred). The serial data is composed of two DAC address bits (A1, A0) and two control
DOUT*
MISO*
SS
DIN
MOSI
MAX5500 MAX5501
SCLK
SCK
SPI/QSPI PORT
CS
I/O
SCLK
SK
CPOL = 0, CPHA = 0 *THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX5500/MAX5501, BUT CAN BE USED FOR READBACK PURPOSES.
DIN
SO
MAX5500 MAX5501
Figure 3. Connections for SPI/QSPI
DOUT* SI* MICROWIRE PORT MSB.................................................................................................................................LSB CS I/O 16 BITS OF SERIAL DATA ADDRESS CONTROL DATA BITS MSB...........................................................................................LSB BITS BITS
*THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX5500/MAX5501, BUT CAN BE USED FOR READBACK PURPOSES.
A1
A0
C1
C0
D11..............................................................................................D0 12 DATA BITS
4 ADDRESS/ CONTROL BITS
Figure 2. Connections for MICROWIRE
Figure 4. Serial-Data Format
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Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface
Table 1. Serial-Interface Programming Commands
16-BIT SERIAL WORD A1 0 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 A0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 C1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 1 1 C0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D11................D0 MSB LSB 12-bit DAC data 12-bit DAC data 12-bit DAC data 12-bit DAC data 12-bit DAC data 12-bit DAC data 12-bit DAC data 12-bit DAC data XXXXXXXXXXXX 12-bit DAC data XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX FUNCTION
MAX5500/MAX5501
Load input register A; DAC registers unchanged. Load input register B; DAC registers unchanged. Load input register C; DAC registers unchanged. Load input register D; DAC registers unchanged. Load input register A; all DAC registers updated. Load input register B; all DAC registers updated. Load input register C; all DAC registers updated. Load input register D; all DAC registers updated. Update all DAC registers from their respective input registers (startup). Load all DAC registers from shift register (startup). Shutdown (provided PDL = 1) UPO goes low (default) UPO goes high No operation (NOP) to DAC registers Mode 1, DOUT clocked out on SCLK's rising edge. All DAC registers updated. Mode 0, DOUT clocked out on SCLK's falling edge. All DAC registers updated (default).
Figure 5 shows the serial-interface timing requirements. The CS input must be low to enable the DAC's serial interface. When CS is high, the interface control circuitry is disabled. CS must go low for at least tCSS before the rising serial clock (SCLK) edge to properly clock in the first bit. When CS is low, data is clocked into the internal shift register through the serial data input (DIN) on the rising edge of SCLK. The maximum guaranteed clock frequency is 10MHz. Data is latched into the appropriate input/DAC registers on the rising edge of CS. The programming command "load-all-dacs-from-shiftregister" allows all input and DAC registers to be simultaneously loaded with the same digital code from the input shift register. The no operation (NOP) command leaves the register contents unaffected. This feature is used in a daisy-chain configuration (see the Daisy Chaining Devices section).
The command to change the clock edge on which serial data is shifted out of DOUT also loads data from all input registers to their respective DAC registers.
Serial-Data Output (DOUT)
The serial-data output, DOUT, is the internal shift register's output. The MAX5500/MAX5501 can be programmed so that data is clocked out of DOUT on the rising edge of SCLK (mode 1) or the falling edge (mode 0). In mode 0, output data at DOUT lags input data at DIN by 16.5 clock cycles, maintaining compatibility with MICROWIRE, SPI/QSPI, and other serial interfaces. In mode 1, output data lags input data by 16 clock cycles. On power-up, DOUT defaults to mode 0 timing.
User-Programmable Logic Output (UPO)
The user-programmable logic output, UPO, allows an external device to be controlled through the MAX5500/MAX5501 serial interface (Table 1).
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Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX5500/MAX5501
CS COMMAND EXECUTED 1 DIN DOUT (MODE 0) A1 A0 C1 C0 D11 D10 D9 8 D8 D7 9 D6 D5 D4 D3 D2 D1 16 D0
SCLK
DATA PACKET (N) A1 A0 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A1
MSB FROM PREVIOUS WRITE DATA PACKET (N-1) DOUT (MODE 1) A1 A0 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA PACKET (N) A1
MSB FROM PREVIOUS WRITE DATA PACKET (N-1) DATA PACKET (N)
Figure 5. Serial-Interface Timing Diagram
CS tCSO SCLK tDS DIN tDO1 DOUT tDO2 tDH tCSS tCL tCH tCP tCSH tCS1
tCSW
Figure 6. Detailed Serial-Interface Timing Diagram
Power-Down Lockout (PDL)
Drive power-down lockout, PDL, low to disable software shutdown. When in shutdown, transitioning PDL from high to low wakes up the device with the output set to the state prior to shutdown. Use PDL to asynchronously wake up the device.
Daisy Chaining Devices
The MAX5500/MAX5501 can be daisy chained by connecting DOUT of one device to DIN of another device (Figure 7).
Each DOUT output of the MAX5500/MAX5501 includes an internal active pullup. The sink/source capability of DOUT determines the time required to discharge/charge a capacitive load. See the serial-data-out VOH and VOL specifications in the Electrical Characteristics. Figure 8 shows an alternate method of connecting several MAX5500/MAX5501 devices. In this configuration, the data bus is common to all devices. Data is not shifted through a daisy chain. More I/O lines are required in this configuration because a dedicated chip-select input (CS) is required for each IC.
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Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX5500/MAX5501
MAX5500
SCLK DIN CS SCLK MAX5501 DIN CS
MAX5500
SCLK MAX5501 DOUT DIN
CS
MAX5500
SCLK MAX5501 DOUT DIN
CS TO OTHER SERIAL DEVICES
DOUT
Figure 7. Daisy Chaining MAX5500/MAX5501
DIN SCLK CS1 CS2 CS3
TO OTHER SERIAL DEVICES
CS
CS
CS
MAX5500 MAX5501
SCLK DIN SCLK DIN
MAX5500 MAX5501
SCLK DIN
MAX5500 MAX5501
Figure 8. Multiple MAX5500/MAX5501 Devices Sharing a Common DIN Line
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Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX5500/MAX5501
Applications Information
Unipolar Output
For a unipolar output, the output voltages and the reference inputs are of the same polarity. Figure 9 shows the MAX5500/MAX5501 unipolar output circuit, which is also the typical operating circuit. Table 2 lists the unipolar output codes. See Figure 10 for rail-to-rail outputs. Figure 10 shows the MAX5500/MAX5501 with the output amplifiers configured with a closed-loop gain of +2 to provide 0 to 5V full-scale range with a 2.5V external reference voltage.
Bipolar Output
Figure 11 shows the MAX5500/MAX5501 configured for bipolar operation. VOUT = VREF [(2NB/4096) - 1] where NB is the numeric value of the DAC's binary input code. Table 3 shows digital codes (offset binary) and corresponding output voltages for the circuit of Figure 11.
MAX5500 MAX5501
REFERENCE INPUTS REFAB DAC A OUTA FBB DAC B OUTB FBC REFCD +5V VDD FBA
Table 2. Unipolar Code Table
DAC CONTENTS MSB LSB 1111 1111 1111 ANALOG OUTPUT 4095 +VREF ( ------ ) 4096 2049 +VREF ( ------ ) 4096 2048 +VREF +VREF ( ------ )= -------- 4096 2 2047 +VREF ( ------ ) 4096 1 +VREF ( ------ ) 4096 0V
1000
0000
0001
DAC C OUTC FBD DAC D OUTD AGND DGND
1000
0000
0000
0111
1111
1111
0000 0000
0000 0000
0001 0000
Figure 9. Unipolar Output Circuit
REFERENCE INPUTS
+5V VDD FBA 10k 10k
Table 3. Bipolar Code Table
DAC CONTENTS MSB LSB 1111 1000 1000 0111 0000 0000 1111 0000 0000 1111 0000 0000 1111 0001 0000 1111 0001 0000
1 4096
MAX5500 MAX5501
REFAB
REFCD
ANALOG OUTPUT 2047 +VREF ( ------ ) 2048 1 +VREF ( ------ ) 2048 0V 1 -VREF ( ------ ) 2048 2047 -VREF ( ------ ) 2048 2048 -VREF ( ------ ) = -VREF 2048
VREFAB = VREFCD = 2.5V
DAC A
OUTA FBB 10k 10k
DAC B OUTB FBC 10k 10k DAC C OUTC FBD 10k 10k DAC D OUTD AGND DGND
Note: 1 LSB = (VREF) (
12
)
Figure 10. Unipolar Rail-to-Rail Output Circuit
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Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface
Digitally Programmable Current Source
The circuit of Figure 12 places an npn transistor (2N3904 or similar) within the op-amp feedback loop to implement a digitally programmable, unidirectional current source. This circuit drives 4mA to 20mA current loops, which are commonly used in industrial-control applications. The output current is calculated with the following equation: IOUT = (VREF/R) x (NB/4096) where NB is the numeric value of the DAC's binary input code and R is the sense resistor shown in Figure 12. For rated MAX5500/MAX5501 performance, limit VREFAB/ VREFCD to 1.4V below VDD. Bypass VDD with a 4.7F capacitor in parallel with a 0.1F capacitor to AGND. Use short lead lengths and place the bypass capacitors as close as possible to the supply inputs.
MAX5500/MAX5501
Grounding and Layout Considerations
Digital or AC transient signals between AGND and DGND create noise at the analog outputs. Connect AGND and DGND together at the DAC, and then connect this point to the highest-quality ground available. Good PCB ground layout minimizes crosstalk between DAC outputs, reference inputs, and digital inputs. Reduce crosstalk by keeping analog lines away from digital lines. Do not use wire-wrapped boards.
Power-Supply Considerations
On power-up, all input and DAC registers are cleared (set to zero code) and DOUT is in mode 0 (serial data is shifted out of DOUT on the clock's falling edge).
Chip Information
PROCESS: BiCMOS
R1 REF_
R2 REF_ VL
+5V
FB_ DAC_
MAX5500 MAX5501
OUT_
IOUT 2N3904
VOUT
DAC OUT_
-5V
FB_
MAX5500 MAX5501
R1 = R2 = 10k 0.1%
R
Figure 11. Bipolar Output Circuit
Figure 12. Digitally Progammable Current Source
______________________________________________________________________________________
13
Low-Power, Quad, 12-Bit Voltage-Output DACs with Serial Interface MAX5500/MAX5501
Pin Configuration
TOP VIEW +
AGND 1 FBA 2 OUTA 3 OUTB 4 FBB 5 REFAB 6 CL 7 CS 8 20 VDD 19 FBD 18 OUTD 17 OUTC
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 20 SSOP PACKAGE CODE A20-2 DOCUMENT NO. 21-0056
MAX5500 MAX5501
16 FBC 15 REFCD 14 PDL 13 UPO 12 DOUT 11 DGND
DIN 9 SCLK 10
SSOP
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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